The present invention relates to a stack-gate flash memory cell and its flash memory array and, more particularly, to a stack-gate flash cell structure having a high coupling ratio and its contactless flash memory arrays.
A stack-gate flash memory cell is known to be a one-transistor cell, in which a gate length of the cell can be defined to be a minimum feature size (F) of technology used. As a consequence, the stack-gate flash memory cell is often used in a high-density flash memory system. The stack-gate flash memory cell can be configured into different array architectures such as NAND, NOR, and AND, based on the basic logic function.
For a NAND-type flash memory array, the stack-gate flash memory cell is connected in series with common-source/drain diffusion regions. In general, a unit cell size of a NAND-type flash memory array is small, but the read speed is slow due to the series resistance of the configuration. For a NOR-type flash memory array, the read speed is much faster, but the unit cell size is larger than that of a NAND-type flash memory array due to the bit-line contacts, and the punch-through effect becomes a major concern for further device scaling if the channel hot-electron injection (CHEI) is used as a programming method. For a AND-type flash memory array, the stack-gate flash memory cells are connected in parallel through the buried source/drain diffusion lines, the unit cell size is slightly larger than that of a NAND-type flash memory array but is smaller than of a NOR-type flash memory array, and the read speed is faster than that of a NAND-type flash memory array and is slower than that a NOR-type flash memory array.
FIG. 1A shows a schematic top plan view of a conventional NOR-type flash memory array, in which a cross-sectional view along a A-Axe2x80x2 line is shown in FIG. 1B and a cross-sectional view along a B-Bxe2x80x2 line is shown in FIG. 1C. As shown in FIG. 1A, an active region 101b is defined on a semiconductor substrate 100 by a first masking photoresist step with isolation regions 101a being formed outside of the active region 101b; the floating-gate layers 103 together with the control-gate layers 105 are simultaneously patterned by a third masking photoresist step, in which the width of the floating-gate layers 103 is patterned by a second masking photoresist step and the control-gate layer 105 is acted as a word line (WL1 or WL2); the active regions 101b outside of the control-gate layers 105 are implanted with a high dose of doping impurities in a self-aligned manner to form common-source diffusion regions 106a and common-drain diffusion regions 106b; an interlayer dielectric layer 107 is formed over a formed structure surface and is then planarized; the contact holes 108 are formed over the common-drain diffusion regions 106b by a fourth masking photoresist step; a tungsten plug being lined with a barrier metal layer 108a is formed to fill each of the contact holes 108 and is planarized; and the metal layers 109 being patterned by a fifth masking photoresist step are formed over the tungsten plugs 108a to act as the bit lines (BL1 and BL2). It is clearly seen that a NOR-type flash memory array shown in FIG. 1A needs at least five masking photoresist steps and a unit cell (UC) size as indicated by a dash square is at least 9F2.
FIG. 1B shows a cross-sectional view along a A-Axe2x80x2 line shown in FIG. 1A, in which two stack-gate structures are formed on a semiconductor substrate 100. Each of the stack-gate structures comprises a control-gate layer 105 over an intergate dielectric layer 104 being formed over a floating-gate layer 103; a tunneling dielectric layer 102 being formed under the floating-gate layer 103 and on the semiconductor substrate 100; and a common-source diffusion region 106a and a common-drain diffusion region 106b being formed in surface portions of the semiconductor substrate 100 in a self-aligned manner by using the stack-gate structures as implantation masks. A contact hole 108 being filled with a tungsten plug 108a is formed over a surface portion of the common-drain diffusion region 106b, and a metal layer 109 acting as a bit line is formed over the interlayer dielectric layer 107 and is connected to the tungsten plug 108a. It is clearly seen from FIG. 1B that the fourth masking photoresist step is required to form the contact hole 108 between two stack-gate structures and misalignment of the contact hole 108 would result in asymmetric parasitic drain resistance for nearby stack-gate structures.
FIG. 1C shows a cross-sectional view along a B-Bxe2x80x2 line shown in FIG. 1A, in which a floating-gate layer 103 is formed over a tunneling dielectric layer 102 and two field-oxide (FOX) layers 110a to increase the coupling ratio; an intergate dielectric layer 104 is formed over the floating-gate layer 103 and portions of the field-oxide layers 101a; a control-gate layer 105 is formed over the intergate dielectric layer 104; an interlayer dielectric layer 107 is formed over the control-gate layer 107; and a metal layer 109 is formed over a surface portion of the interlayer dielectric layer 107 and is aligned above a middle portion of the tunneling dielectric layer 102. It is clearly seen from FIG. 1C that the second masking photoresist step is required to pattern the width of the floating-gate layer 103 and misalignment between the floating-gate layer 103 with respect to the tunneling dielectric layer 102 in the active region 101b would occur and will result in asymmetric field distribution near two edges during programming and erasing.
It is, therefore, a major objective of the present invention to offer a stack-gate flash cell structure with an integrated floating-gate being formed along a channel-length direction to largely increase the coupling ratio of a cell.
It is another objective of the present invention to offer a parallel common-source/drain diffusion bit-lines array being fabricated with less masking photoresist steps.
It is a further objective of the present invention to offer a parallel common-source/drain diffusion bit-lines array having a unit cell size of 4F2.
Other objectives and advantages of the present invention will be more apparent in a later description.
The present invention discloses a stack-gate flash cell structure and its contactless flash memory arrays. The stack-gate flash cell structure comprises a gate region being formed between common-source/drain regions, wherein the gate region being defined by a first masking photoresist step is formed on a semiconductor substrate of a first conductivity type. Each of the common-source/drain regions comprises a common-source/drain diffusion region being formed in a surface portion of the semiconductor substrate, an etched-back planarized silicon dioxide layer over a first portion of a tunneling dielectric layer being formed on the common-source/drain diffusion region, and a pair of extended floating-gate spacers being formed over side portions of the etched-back planarized silicon dioxide layer in each of the common-source/drain regions. The gate region comprises a major floating-gate being formed over a second portion of the tunneling dielectric layer and integrated with nearby two extended floating-gate spacers to form an integrated floating-gate, wherein an implant region of the first conductivity type comprising a shallow implant region for threshold-voltage adjustment and a deep implant region for forming a punch-through stop can be formed in a middle surface portion of the semiconductor substrate in the gate region. A word line together with an intergate dielectric layer is formed over the integrated floating-gate and the etched-back planarized silicon dioxide layer between the pair of extended floating-gate spacers in each of the common-source/drain regions, wherein the word line, the intergate dielectric layer, and the integrated floating-gate are simultaneously patterned and etched by a second masking photoresist step. A cell isolation region comprising an isolation implant region of the first conductivity type or a shallow trench isolation region being formed in a surface portion of the semiconductor substrate outside of the word line and between the common-source/drain regions.
The contactless flash memory array of the present invention comprises a plurality of gate regions being defined by a first masking photoresist step, wherein each of the plurality of gate regions is formed over a semiconductor substrate of a first conductivity type between common-source/drain regions. Each of the common-source/drain regions comprises a common-source/drain diffusion region being formed in a surface portion of the semiconductor substrate to act as a buried diffusion bit line, an etched-back planarized silicon dioxide layer over a first portion of a tunneling dielectric layer being formed over the common-source/drain diffusion region, and a plurality of paired extended floating-gate spacers being formed over side portions of the etched-back planarized silicon dioxide layer. Each of the plurality of gate regions comprises a plurality of major floating-gates being formed over a second portion of the tunneling dielectric layer and integrated with nearby extended floating-gate spacers to form a plurality of integrated floating-gates, wherein an implant region of the first conductivity type comprising a shallow implant region for threshold-voltage adjustment and a deep implant region for forming a punch-through stop can be formed in a middle surface portion of the semiconductor substrate under each of the plurality of major floating-gates. A plurality of word lines together with a plurality of intergate dielectric layers are formed over the plurality of integrated floating-gates and the etched-back planarized silicon dioxide layers between the plurality of paired extended floating-gate spacers in each of the common-source/drain regions, wherein the plurality of word lines, the plurality of intergate dielectric layers, and the plurality of integrated floating-gates are simultaneously patterned and etched by a second masking photoresist step. A plurality of cell isolation regions comprising a plurality of isolation implant regions or a plurality of shallow trench isolation regions are formed in surface portions of the semiconductor substrate outside of the plurality of word lines and between the common-source/drain regions.